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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">PMSIDR_EL1, Sampling Profiling ID Register</h1><p>The PMSIDR_EL1 characteristics are:</p><h2>Purpose</h2>
        <p>Describes the Statistical Profiling implementation to software</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMSIDR_EL1 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>PMSIDR_EL1 is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_26">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="6"><a href="#fieldset_0-63_26">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-25_25">CRR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-24_24">PBT</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">Format</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">CountSize</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">MaxSize</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">Interval</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_7">FDS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-6_6">FnE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-5_5">ERnd</a></td><td class="lr" colspan="1"><a href="#fieldset_0-4_4">LDS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-3_3">ArchInst</a></td><td class="lr" colspan="1"><a href="#fieldset_0-2_2">FL</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1">FT</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">FE</a></td></tr></tbody></table><h4 id="fieldset_0-63_26">Bits [63:26]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-25_25">CRR, bit [25]</h4><div class="field">
      <p>Call Return branch records. Defined values are:</p>
    <table class="valuetable"><tr><th>CRR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Operation Type packets for branches do not contain Call Return information.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Operation Type packets for branches contain Call Return information.</p>
        </td></tr></table>
      <p><span class="xref">FEAT_SPE_CRR</span> implements the functionality identified by the value 1.</p>
    </div><h4 id="fieldset_0-24_24">PBT, bit [24]</h4><div class="field">
      <p>Previous branch target Address packet. Defined values are:</p>
    <table class="valuetable"><tr><th>PBT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Previous branch target Address packet not supported.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Previous branch target Address packet support implemented.</p>
        </td></tr></table>
      <p><span class="xref">FEAT_SPEv1p2</span> implements the <span class="arm-defined-word">OPTIONAL</span> functionality identified by the value 1.</p>
    </div><h4 id="fieldset_0-23_20">Format, bits [23:20]</h4><div class="field">
      <p>Defines the format of the sample records. Defined values are:</p>
    <table class="valuetable"><tr><th>Format</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Format 0.</p>
        </td></tr></table>
      <p>All other values are reserved.</p>
    </div><h4 id="fieldset_0-19_16">CountSize, bits [19:16]</h4><div class="field">
      <p>Defines the size of the counters.</p>
    <table class="valuetable"><tr><th>CountSize</th><th>Meaning</th><th>Applies when</th></tr><tr><td class="bitfield">0b0010</td><td>
          <p>12-bit saturating counters.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>16-bit saturating counters.</p>
        </td><td>From Armv8.8</td></tr></table><p>All other values are reserved.</p>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-15_12">MaxSize, bits [15:12]</h4><div class="field">
      <p>Defines the largest size for a single record, rounded up to a power-of-two. If this is the same as the minimum alignment (<a href="AArch64-pmbidr_el1.html">PMBIDR_EL1</a>.Align), then each record is exactly this size. Defined values are:</p>
    <table class="valuetable"><tr><th>MaxSize</th><th>Meaning</th></tr><tr><td class="bitfield">0b0100</td><td>
          <p>16 bytes.</p>
        </td></tr><tr><td class="bitfield">0b0101</td><td>
          <p>32 bytes.</p>
        </td></tr><tr><td class="bitfield">0b0110</td><td>
          <p>64 bytes.</p>
        </td></tr><tr><td class="bitfield">0b0111</td><td>
          <p>128 bytes.</p>
        </td></tr><tr><td class="bitfield">0b1000</td><td>
          <p>256 bytes.</p>
        </td></tr><tr><td class="bitfield">0b1001</td><td>
          <p>512 bytes.</p>
        </td></tr><tr><td class="bitfield">0b1010</td><td>
          <p>1KB.</p>
        </td></tr><tr><td class="bitfield">0b1011</td><td>
          <p>2KB.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>The values <span class="binarynumber">0b0100</span> and <span class="binarynumber">0b0101</span> are not permitted for an implementation.</p>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-11_8">Interval, bits [11:8]</h4><div class="field">
      <p>Recommended minimum sampling interval. This provides guidance from the implementer to the smallest minimum sampling interval, N. Defined values are:</p>
    <table class="valuetable"><tr><th>Interval</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>256.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>512.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>768.</p>
        </td></tr><tr><td class="bitfield">0b0100</td><td>
          <p>1,024.</p>
        </td></tr><tr><td class="bitfield">0b0101</td><td>
          <p>1,536.</p>
        </td></tr><tr><td class="bitfield">0b0110</td><td>
          <p>2,048.</p>
        </td></tr><tr><td class="bitfield">0b0111</td><td>
          <p>3,072.</p>
        </td></tr><tr><td class="bitfield">0b1000</td><td>
          <p>4,096.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-7_7">FDS, bit [7]</h4><div class="field">
      <p>Filter by data source. Defined values are:</p>
    <table class="valuetable"><tr><th>FDS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="AArch64-pmsdsfr_el1.html">PMSDSFR_EL1</a> is not implemented and <a href="AArch64-pmsfcr_el1.html">PMSFCR_EL1</a>.FDS is <span class="arm-defined-word">RES0</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="AArch64-pmsdsfr_el1.html">PMSDSFR_EL1</a> and <a href="AArch64-pmsfcr_el1.html">PMSFCR_EL1</a>.FDS are implemented.</p>
        </td></tr></table>
      <p><span class="xref">FEAT_SPE_FDS</span> implements the functionality identified by the value 1.</p>
    </div><h4 id="fieldset_0-6_6">FnE, bit [6]</h4><div class="field">
      <p>Filtering by events, inverted. Defined values are:</p>
    <table class="valuetable"><tr><th>FnE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="AArch64-pmsnevfr_el1.html">PMSNEVFR_EL1</a> is not implemented and <a href="AArch64-pmsfcr_el1.html">PMSFCR_EL1</a>.FnE is <span class="arm-defined-word">RES0</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="AArch64-pmsnevfr_el1.html">PMSNEVFR_EL1</a> and <a href="AArch64-pmsfcr_el1.html">PMSFCR_EL1</a>.FnE are implemented.</p>
        </td></tr></table>
      <p>FEAT_SPEv1p2 implements the functionality identified by the value 1.</p>
    </div><h4 id="fieldset_0-5_5">ERnd, bit [5]</h4><div class="field">
      <p>Defines how the random number generator is used in determining the interval between samples, when enabled by <a href="AArch64-pmsirr_el1.html">PMSIRR_EL1</a>.RND. Defined values are:</p>
    <table class="valuetable"><tr><th>ERnd</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The random number is added at the start of the interval, and the sample is taken and a new interval started when the combined interval expires.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The random number is added and the new interval started after the interval programmed in <a href="AArch64-pmsirr_el1.html">PMSIRR_EL1</a>.INTERVAL expires, and the sample is taken when the random interval expires.</p>
        </td></tr></table>
      <p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-4_4">LDS, bit [4]</h4><div class="field">
      <p>Data source indicator for sampled load instructions. Defined values are:</p>
    <table class="valuetable"><tr><th>LDS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Loaded data source not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Loaded data source implemented.</p>
        </td></tr></table>
      <p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-3_3">ArchInst, bit [3]</h4><div class="field">
      <p>Architectural instruction profiling. Defined values are:</p>
    <table class="valuetable"><tr><th>ArchInst</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Micro-op sampling implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Architecture instruction sampling implemented.</p>
        </td></tr></table>
      <p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-2_2">FL, bit [2]</h4><div class="field">
      <p>Filtering by latency. This bit is RAO.</p>
    </div><h4 id="fieldset_0-1_1">FT, bit [1]</h4><div class="field">
      <p>Filtering by operation type. This bit is RAO.</p>
    </div><h4 id="fieldset_0-0_0">FE, bit [0]</h4><div class="field">
      <p>Filtering by events. This bit is RAO.</p>
    </div><div class="access_mechanisms"><h2>Accessing PMSIDR_EL1</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, PMSIDR_EL1</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b1001</td><td>0b1001</td><td>0b111</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) &amp;&amp; MDCR_EL3.NSPBE != SCR_EL3.NSE)) then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') &amp;&amp; HDFGRTR_EL2.PMSIDR_EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; MDCR_EL2.TPMS == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) &amp;&amp; MDCR_EL3.NSPBE != SCR_EL3.NSE)) then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        X[t, 64] = PMSIDR_EL1;
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) &amp;&amp; MDCR_EL3.NSPBE != SCR_EL3.NSE)) then
        UNDEFINED;
    elsif HaveEL(EL3) &amp;&amp; (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) &amp;&amp; MDCR_EL3.NSPBE != SCR_EL3.NSE)) then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        X[t, 64] = PMSIDR_EL1;
elsif PSTATE.EL == EL3 then
    X[t, 64] = PMSIDR_EL1;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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